1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a dynamic random access memory device which employs a so-called VSS precharge method in which a bit line connected to a memory cell is precharged to the ground voltage.
2. Description of the Related Art
Various bit line precharge methods applied to DRAM devices have been proposed. Examples of such methods are a Vii precharge method and 1/2.cndot.Vii precharge method. The Vii precharge method precharges the bit lines to an internal power supply voltage Vii. The 1/2.cndot.Vii precharge method precharges the bit lines to half the internal power supply voltage Vii. The 1/2.cndot.Vii precharge method consumes a smaller amount of power than the Vii precharge method, and is widely used as compared thereto.
FIG. 1 is a circuit diagram of a sense amplifier provided in a DRAM device. The sense amplifier includes pMOS (p-channel) transistors 1 and 2 serving as pull-up elements, and nMOS (n-channel) transistor 3 and 4 serving as pull-down elements. These transistors are connected in a cross-coupled formation. The sense amplifier is connected to a pair of bit lines BL and /BL, and is supplied with sense amplifier driving voltages PSA and NSA.
FIG. 2 is a waveform diagram of a sense amplifying operation in a DRAM device which has the sense amplifier shown in FIG. 1 and employs the 1/2.cndot.Vii precharge method. The sense amplifier driving voltages PSA and NSA are set equal to 1/2.cndot.Vii before data is read from a memory cell. Further, the bit lines BL and /BL are precharged to 1/2.cndot.Vii by a bit line precharge circuit (not shown).
If a memory cell connected to the bit line BL is selected and stores high-level data (that is, the selected memory cell stores a charge), the voltage of the bit line BL is changed to 1/2.cndot.Vii+.DELTA.V where .DELTA.V is a fine voltage produced so that the charge stored in the cell capacitor of the selected memory cell is divided into parts stored in the cell capacitor and the bit line BL.
Subsequently, the sense amplifier driving voltages PSA and NSA are set equal to Vii and VSS, respectively. Thus, the voltage of the bit line /BL is pulled down from the voltage 1/2.cndot.Vii and becomes equal to the ground voltage VSS due to the function of the nMOS transistor 4. The voltage of the bit line BL is pulled up from the 1/2.cndot.Vii+.DELTA.V and becomes equal to the internal power supply voltage Vii.
If the internal power supply voltage Vii is attempted to be reduced in the case where the above-mentioned 1/2.cndot.Vii precharge method, the following disadvantage will occur. In this case, the gate-source voltage Vgs of the pMOS transistors 1 and 2 and the nMOS transistors 3 and 4 is reduced. Thus, it takes a longer time to amplify the fine voltage .DELTA.V between the bit lines BL and /BL.
In contrast, the VSS precharge method in which the bit lines BL and /BL are precharged to the ground voltage VSS can speed up the operation of the sense amplifier.
FIG. 3 is a waveform diagram of an operation of the sense amplifier shown in FIG. 1 provided in the DRAM device employing the VSS precharge method. The sense amplifier driving voltage PSA is set equal to the ground voltage VSS before data is read from the memory cell. In addition, the bit lines BL and /BL are precharged to the ground voltage VSS.
When a memory cell connected to the bit line BL is selected and stores high-level data (that is, the selected memory cell stores a charge), the voltage of the bit line BL becomes equal to .DELTA.V, and the voltage of the bit line /BL becomes equal to .DELTA.Vd generated by a dummy cell (&lt;.DELTA.V). Subsequently, the sense amplifier driving voltage PSA is set equal to Vii. Thus, the voltages of the bit lines BL and /BL are increased. Then, the sense amplifier driving voltage NSA becomes equal to VSS, and the MOS transistors 1, 2, 3 and 4 are turned ON, OFF, OFF and ON, respectively. As a result, the voltages of the bit lines BL and /BL become equal to Vii and VSS.
When the above-mentioned VSS precharge method is employed, the gate-source voltage Vgs of the pMOS transistors 1 and 2 can be increased, and thus it becomes possible to reduce the time necessary to amplify the fine voltage .DELTA.V-.DELTA.Vd between the bit lines BL and /BL.
FIG. 4 is a circuit diagram of a memory cell of the DRAM device. The memory cell includes a cell capacitor 6 serving as a storage element, and a cell transistor 5 formed of an nMOS transistor for controlling a charge transfer. The gate (control electrode) of the cell transistor 5 is connected to a word line WL, and the source (a first current input/output electrode) thereof is connected to a bit line BL. The drain (a second current input/output electrode) of the cell transistor 5 is connected to one end of the cell capacitor 6, the other end of which is grounded.
When the VSS precharge method is employed and high-level data (logic "1") is written into the memory cell, the voltages of the word line WL and the bit line BL are respectively set equal to SVii and Vii, and the voltage of a storage node 7 is set equal to Vii. When low-level data (logic "0") is written into the memory cell, the voltages of the word line WL and the bit line BL are respectively set equal to SVii and VSS, and the voltage of the storage node 7 is set equal to VSS. The voltage SVii is a boosted voltage obtained by stepping up the internal power supply voltage Vii by means of a voltage boost circuit (not shown), and is greater than Vii+VTHn where VTHn is the threshold voltage of the nMOS transistor).
In the case where the VSS precharge method is employed, when the voltage of the bit line BL is set equal to VSS in a state in which the memory cell shown in FIG. 4 is not selected, the gate-source voltage Vgs of the cell transistor 5 becomes 0 V. Hence, if the high-level data is stored in the storage node 7, a leakage current i flows from the drain to source of the cell transistor 5 in accordance with a source-drain current ids vs. gate source voltage Vgs characteristic shown in FIG. 5.
Hence, the voltage drop of the storage node 7 is facilitated, and a refresh time tREF is degraded. In addition, the voltage appearing on the bit line BL is lower than a voltage .DELTA.V which originally appears on the bit line BL when there is no leakage in the cell with the internal power supply voltage Vii applied thereto. Thus, the operational margin of the sense amplifier with respect to high-level data is reduced.
In the case where the 1/2.cndot.Vii precharge method is employed, when the potential of the storage node 7 is 0 V, the gate-source voltage Vgs is 0 V. Hence, the potential of the storage node 7 is increased due to the leakage current flowing in the cell transistor 5. However, in this case, the gate-drain voltage Vgs becomes negative, and the back bias is enhanced. As a result, the leakage current flowing in the cell transistor 5 can be suppressed.